// --------------------------------------------------------------------------- // sample_sync.sv — QX-250 FPGA block B5 (sample-sync & timestamp) // FPGA-QX250-001 · traces REQ-CTRL-004, functional F7 // // The single timebase for the sense/control chain. All ticks are clock-ENABLES // off clk_sys (single-clock design — see B8), never separate clocks: // * us_tick — 1 MHz, drives the free-running microsecond `timestamp` // * imu_tick — IMU acquisition rate (default 8 kHz); starts a B3 burst // * baro_tick — barometer rate (default 50 Hz); starts a B4 read // * imu_sample_ts — `timestamp` latched at imu_tick, so software knows exactly // WHEN the sample was taken → time-coherent sensor fusion. // // Divisors are parameters (defaults sized for 48 MHz) so the testbench can shrink // them for fast simulation without changing the logic. // --------------------------------------------------------------------------- `timescale 1ns/1ps `default_nettype none module sample_sync #( parameter int US_DIV = 48, // clk_sys/1MHz (48 MHz → 48) parameter int IMU_DIV = 6000, // clk_sys/8kHz (48 MHz → 6000) parameter int BARO_DIV = 960000 // clk_sys/50Hz (48 MHz → 960000) ) ( input wire clk, input wire rst_n, output reg us_tick, output reg [31:0] timestamp, // microseconds since reset (wraps ~71 min) output reg imu_tick, output reg baro_tick, output reg [31:0] imu_sample_ts ); reg [31:0] uc, ic, bc; always_ff @(posedge clk or negedge rst_n) begin if (!rst_n) begin uc <= 0; ic <= 0; bc <= 0; us_tick <= 1'b0; imu_tick <= 1'b0; baro_tick <= 1'b0; timestamp <= 32'd0; imu_sample_ts <= 32'd0; end else begin us_tick <= 1'b0; imu_tick <= 1'b0; baro_tick <= 1'b0; // 1 MHz microsecond timebase if (uc == US_DIV - 1) begin uc <= 0; us_tick <= 1'b1; timestamp <= timestamp + 32'd1; end else uc <= uc + 1; // IMU acquisition tick (+ timestamp latch for this sample) if (ic == IMU_DIV - 1) begin ic <= 0; imu_tick <= 1'b1; imu_sample_ts <= timestamp; end else ic <= ic + 1; // Barometer acquisition tick if (bc == BARO_DIV - 1) begin bc <= 0; baro_tick <= 1'b1; end else bc <= bc + 1; end end endmodule `default_nettype wire