// ---------------------------------------------------------------------------
// clk_reset.sv  —  QX-250 FPGA block B8 TOP (clock + reset generation)
// FPGA-QX250-001 · feeds clk_sys/rst_n to B1..B9
//
// Composes qx_pll + reset_sync into the single clock/reset source for the whole
// design. Output contract:
//   clk_sys : 48 MHz system clock (exact DShot600 timing — see B1)
//   rst_n   : active-low reset, async-assert / sync-deassert, held until PLL lock
//   locked  : PLL lock status (also surfaced to status/telemetry via B9)
//
// Design choice: SINGLE clock domain. SPI SCLK (B3) and the sample ticks
// (8 kHz IMU / 50 Hz baro / 1 µs global, B5) are generated as clock-ENABLES off
// clk_sys, not as separate generated clocks — simpler timing closure and far
// less CDC to verify. Async INPUT pins are synchronized with cdc_sync2.
// ---------------------------------------------------------------------------
`timescale 1ns/1ps
`default_nettype none

module clk_reset #(
    parameter int CLK_IN_HZ   = 24_000_000,
    parameter int CLK_SYS_HZ  = 48_000_000,
    parameter int RST_STAGES  = 3,
    parameter int LOCK_CYCLES = 64
) (
    input  wire clk_in,        // board oscillator
    input  wire ext_rst_n,     // external / power-on reset, active low (async)
    output wire clk_sys,       // 48 MHz domain clock
    output wire rst_n,         // synchronized domain reset, active low
    output wire locked         // PLL lock (status)
);

    qx_pll #(
        .CLK_IN_HZ   (CLK_IN_HZ),
        .CLK_OUT_HZ  (CLK_SYS_HZ),
        .LOCK_CYCLES (LOCK_CYCLES)
    ) u_pll (
        .clk_in   (clk_in),
        .rst_in_n (ext_rst_n),
        .clk_out  (clk_sys),
        .locked   (locked)
    );

    reset_sync #(
        .STAGES (RST_STAGES)
    ) u_rst (
        .clk         (clk_sys),
        .async_rst_n (ext_rst_n),
        .lock        (locked),
        .rst_n       (rst_n)
    );

endmodule

`default_nettype wire